The present invention relates generally to integrated circuits and integrated circuit design processes, and more particularly to a base transistor structure that may be used to implement programmable cells in integrated circuits.
Standard cell application-specific integrated circuits (ASICs) provide a number of significant advantages over other types of integrated circuits, including more manageable die size, lower piece-part cost, higher performance, and more reliable design flow. The standard cell approach is generally considered preferable to other competing approaches such as custom design and programmable logic. As a result, most existing integrated circuit computer-aided design (CAD) tools, such as place and route tools, are configured for operation with the standard cell approach. In general, CAD tools designed for programmable logic are often incompatible with standard cell tools and may require specially trained experts.
One potential problem associated with the standard cell approach is that non-recurring expense (NRE) and process cycle time for development of a given design may still be unduly high. The principal components of the NRE are the cost of a new lot start and the cost of a new mask set as required to implement changes in a standard cell design. As the transistor technology shrinks in size, the lot start and mask set costs can increase considerably. With regard to process cycle time, ASICs typically undergo several design iterations before qualifying for full production. Reaching production with pure standard cell technology can thus be costly and time consuming at a time when market forces are squeezing costs and shortening development cycles.
A number of techniques have been developed in an attempt to alleviate the above-noted problem of the standard cell approach.
One such technique involves the use of so-called multi-chip shuttles to amortize the lot start and mask set costs over several chips. Basically, a prototype lot is ordered for model production only where there may be four to six individual chips placed on the same wafer and reticle. The drawbacks of this technique include a limited die size for each constituent chip, difficulty in timing and coordination of mask order and other functions across four to six chip projects, and potential saw-apart and packaging problems.
Another known technique involves the embedding of spare standard cell gates in a chip netlist to be used at a later time for design changes. However, these spare gates are generally hand-instantiated into the netlist by the customer, the level of design change supported is extremely limited, and wiring the change into the design can be difficult due to poor cell placement.
A third technique involves embedding programmable logic within a standard cell ASIC. However, as mentioned previously, programmable logic generally requires specialized CAD tools, and thus can create tool interface problems when used in a standard cell ASIC. For example, the use of a gate array place and route tool for a standard cell ASIC will generally require conversion of standard cell tool infrastructure over to the gate array tool and corresponding re-training of standard cell tool users, thereby imposing a high development cost burden on what are typically only a few candidate applications. In addition, the use of programmable logic can create difficult xe2x80x9cfloor planxe2x80x9d issues. Other drawbacks include the fact that programmable gate array density is typically only half to less than half the density of standard cell, which affects die size and thus piece part cost, and can also impact performance.
In view of the foregoing, it is apparent that a need exists in the art for a base transistor structure that is programmable but also fully compatible with standard cell CAD tools.
The present invention solves one or more of the above-noted problems by providing a base transistor structure compatible with standard cell CAD tools.
In accordance with one aspect of the invention, a base transistor structure for use in an integrated circuit includes a number of source regions, a number of drain regions each adjacent to a corresponding one of the source regions, and at least first and second elongated gates. The first and second gates each overlie a corresponding pair of the source and drain regions, and extend longitudinally along a first axis from a first end adjacent one of the source and drain regions to a second end extending past another of the source and drain regions. The first and second gates are separated from one another at the second ends thereof. The base transistor structure is configured so as to be substantially symmetric about the first axis. One or more circuit cells of the integrated circuit can be formed by utilizing multiple base transistor structures of this type arranged immediately adjacent to one another.
By way of example, the base transistor structure may provide a pair of field effect transistors (FETs), i.e., a P-type FET (PFET) and an N-type FET (NFET), suitable for use in otherwise conventional complementary metal-oxide-semiconductor (CMOS) logic circuitry. In such an arrangement, the first and second gates of the base transistor structure correspond to gates of the respective PFET and NFET devices.
In an illustrative embodiment of the invention, the base transistor structure is symmetric about one or more axes, extends only a single grid of a standard cell CAD tool in width. In addition, the above-described split gate base transistor structure is preferably configured in a manner that permits the utilization of gate isolation to separate active transistors in adjacent base transistor structures.
Advantageously, the base transistor structure of the present invention can be used to implement a programmable cell technology that is fully compatible with standard cell CAD tools.